1. Field of the invention
The present invention relates to a synchronized semiconductor memory.
2. Description of related art
Synchronized semiconductor memory devices using dynamic random access memories (DRAM) have been variously designed to operate with a high speed, but in the prior art DRAM, there is a problem that an access time of the DRAM interferes with elevation of the system capacity in a high speed system such as a RISC (reduced instruction set computer) type MPU (microprocessor unit) whose system clock frequency exceeds 100 MHz (10 ns). In order to solve this problem, a semiconductor memory device synchronized with an external clock has been proposed. There are many techniques to realize this synchronized semiconductor memory device. One of these techniques is so called three-stage pipeline. This is a technique which realizes a high speed operation by dividing a reading/writing operation starting a column address receiving, with two latch circuits, into three parts which operate in parallel to one another.
A prior art synchronized semiconductor memory device will now be explained with reference to FIGS. 1 to 4. FIG. 1 is a block diagram illustrating a construction of the prior art synchronized semiconductor memory device, and FIGS. 3 and 4 are timing charts illustrating an operation of the prior art synchronized semiconductor memory device. FIG. 2 is a logic circuit diagram showing a construction of the delay circuit included in the prior art synchronized semiconductor memory device.
In the following explanation, the negation of a chip selection signal CS, a row address strobe signal RAS, a column address strobe signal CAS and a write enable signal WE are indicated as CSB, RASB, CASB and WEB, respectively.
Referring to FIG. 1 and FIG. 3, at a time to an ACTIVE command (in a row address operation command, both of the signals CSB and RASB are at a LOW level, and both of the signals CASB and WE are at a HIGH level) is inputted into input terminals 61. The command is decoded by an input circuit 21, and then latched in circuit (D flip-flop circuit) 22. Furthermore, at the time t0, a clock is inputted from a terminal 62 through an input circuit 34 to an internal clock generating circuit 35.
In the internal clock generating circuit 35, an internal clock signal (1) 36 is generated, and supplied to latch circuits 2, 22 and 31, logic circuits 37 and 43, a writing control circuit 26, a read control circuit 27, and a delay circuit 39. The logic circuit 37 receives the internal clock signal (1) 36 and generates an internal clock signal (2) 38. Furthermore, the delay circuit 39 receives the internal clock signal (1) 36 and other input signals, and generates an internal clock signal (5) 40, an internal clock signal (6) 41, and an internal clock signal (7) 42. Similarly, the logic circuit 43 receives the internal clock signal (1) 36, the internal clock signal (7) 42 supplied from the delay circuit 39, an internal clock signal (3) enable signal 30 outputted from the reading control circuit 27, and generates an internal clock signal (3) 44.
The ACTIVE command as mentioned above is latched in the latch circuit in response to the internal clock signal (1) 36, and the latched active command is supplied to a row address control circuit 13, which in turn generates an "A bank" row address enable signal ARAE 14 and, a "B bank" row address enable signal BRAE 15. Furthermore, a row address ADD(X) inputted into terminals 59 is supplied through an input circuit 1 to the latch circuit (D flip-flop circuit) 2, and then latched in the latch circuit 2 in response to the internal clock signal (1) 36. Thereafter, the latched row address ADD(X) is inputted through a row address buffer 7 into a row decoder 8, which in turn selects a row selection line 9 corresponding to the row address ADD(X).
The synchronized semiconductor memory device shown FIG. 1 is an example of a two-bank constitution. Here, the bank is that a selection and a precharge of a row address can be independently executed in each bank, and the synchronized semiconductor memory containing the two banks has two sets of row address control circuits. As mentioned above, ARAE shown in FIG. 3 is a row address enable signal for the A bank, and BRAE is a row address enable signal for the B bank. When the ACTIVE command signal is inputted, the signals ARAE and BRAE are brought to a HIGH level. The time chart shown in FIG. 3 shows an example in which the A bank is selected and therefore the signal ARAE is at the HIGH level.
Now, a data reading operation will be explained. Referring to FIGS. 1 and 4, at the time t.sub.0, the READ command (the reading operation command: both of the signals CSB and CASB are at a LOW level, both of the signals RASB and WEB are at a HIGH level) is inputted, and the address ADD(A1) is inputted to the terminals 59. Therefore, the READ command is decoded in the input circuit 21 and supplied into the latch circuit 22. The READ command is latched in the latch circuit 22 in response to the internal clock signal (1) 36, and the latched READ command signal 25 is inputted into a column address control circuit 11, and also sent to a read control circuit 27.
The column address control circuit 11 receives the latched READ command signal 25, and generates the column address enable signal 12 to a row address buffer 3. And then, the address ADD(1) is inputted into the latch circuit 2 through the input circuit 1, and latched in response to the internal clock signal (1) 36. The latched address ADDA(1) is inputted into a column decoder 4 through a column address buffer 3. The address ADD(A1) outputted from the column decoder 4 is latched in a latch circuit (D type latch) 5 in response to the internal clock signal (2) 38 outputted from the logic circuit 37, so that a column selection line 6 corresponding to the given address is selected. Thus, memory cells to be read are selected.
Next, the output data read from a memory cell array 10 through sense amplifier 16 is supplied through a R/W (READ/WRITE) bus 17 and amplified by a data amplifier 18, and then, latched in a latch circuit (D type flip-flop circuit) 19 in response to the internal clock signal (3) 44 corresponding to the clock at a time t.sub.2, and outputted to a terminal 60 through an output circuit 20. FIG. 4 shows a time chart in the case of a burst length (bit length to be read and written at the same time) of 4 bits. In FIG. 4, in a series of operations, the operation for the following bits is executed each in one cycle, and these operations are processed in parallel to one another. Namely, the second bit (A2) is executed with three clocks of t.sub.1 .about.t.sub.3, the third bit (A3) is executed with three clocks of t.sub.2 .about.t.sub.4, and the forth bit (A4) is executed with three clocks of t.sub.3 .about.t.sub.5.
Next, a data writing operation will be explained. This operation is almost the same with the reading operation as mentioned above. Referring to FIG. 4, at a time t.sub.8, a WRITE command (writing operation command: the signals CSB, CASB and WEB are at a LOW level, and the signal RASB is at a HIGH level) is inputted from the terminal 61, and a writing data (DQ) is inputted from the terminal 60. In addition, an address ADD(B1) is inputted from the terminal 59.
The WRITE command is decoded by the input circuit 21, and supplied to the latch circuit 22. In the latch circuit 22, the WRITE command is latched in response to the internal clock signal (1) 36 outputted from the internal clock signal generation circuit 35 corresponding to the clock of the time t.sub.8, and a WRITE command signal 24 is outputted from the latch circuit 22, and sent to a writing control circuit 26. The writing data (DQ) inputted from the terminal 51 is sent into a latch circuit (D type flip-flop) 31 through an input circuit 32, and then, is latched in response to the internal clock signal (1) 36 outputted from the internal clock signal generation circuit 35 corresponding to the clock of the time t.sub.8, so that the latched data is sent into the writing control circuit 26.
On the other hand, an address ADD (B1) is inputted into the latch circuit 2 through the input circuit 1, and latched in the latch circuit 2 in response to the internal clock signal (1) 36 outputted from the internal clock signal generation circuit 35 corresponding to the clock of the time t.sub.8. The latched address ADD(B1) is inputted into the column decoder 4 through the column address buffer 3. An address ADD (B1) outputted from the column decoder 4 is latched in the latch circuit 5 in response to the internal clock signal (2) 38 outputted from the logic circuit 37 corresponding to the clock of the time t.sub.9, so that a column selection line 6 corresponding to the given address ADD(B1) is selected. Thus, a memory cell to be written in the memory cell array 10 is selected.
At the same time, in response to the internal clock signal (1) 36 corresponding to the time t.sub.9, the write data (DQ) is outputted from the write control circuit 26 and is sent to the sense amplifier 16 through the R/W (READ/WRITE) bus 17, so that it is amplified by the sense amplifier 16, and is written onto the corresponding memory cell of memory cell array 10. And, the column selection number 9 is brought to a non-selected state in response to the internal clock signal (2) 38 corresponding to the clock of the time t.sub.10, so that the writing operation finishes. Similarly to the reading operation, the writing operation is executed with a unit of 4 bits in parallel. Namely, the second bit (B2) is executed with three clocks of t.sub.9 .about.t.sub.11, the third bit (B3) is executed wit three clocks of t.sub.10 .about.t.sub.12, and the forth bit (B4) is executed with three clocks of t.sub.11 .about.t.sub.13.
The above mentioned operation mode is called "CAS LATENCY 3", because, in the reading operation, data is outputted by a third clock counted after an input of the READ command is inputted. This is set by a mode set circuit 33 when a mode register set cycle (a cycle for setting CAS LATENCY or burst length, etc.: the signals CSB, RASB CASB and WEB are at a LOW level). The operation mode includes "CAS LATENCY 2" and "CAS LATENCY 1" in addition to "CAS LATENCY 3".
In the case of the "CAS LATENCY 2" mode, the internal clock signal (2) 38 is fixed to a HIGH level in order to output the data at the timing of the second clock. Namely, the latch (D type latch circuit) 5 is controlled to allow a signal to always pass therethrough, so the effective number of latches is only two. As the result, the first stage and the second stage of the pipeline operate with the first clock, and the third stage operates with the second clock.
In the case of the "CAS LATENCY 1" mode, if the latch circuit 19 is of a D type latch circuit, both of the internal clock signal (3) 38 and the internal clock signal (3) 44 may be fixed to the HIGH level, but, if the latch circuit 19 is of a D type flipflop circuit, all of the first stage, the second stage and the third stage of the pipeline can be controlled to operate continuously with only one clock, by fixing the internal clock signal (2) 38 to the HIGH level and by generating the internal clock signal (3) 44 from the internal clock signal (7) 42 by using a delay circuit 39. In cases of the "CAS LATENCY 2" and "CAS LATENCY 1", the signals from the writing control circuit 26 and the read control circuit 27 are outputted at timings different from the output timing of those signals in the operating mode "CAS LATENCY 3", and therefore, are generated by using the internal clock signal (5) 40 and the internal clock signal (6) 41 outputted from the delay circuit 39, instead of the internal clock signal (1) 36.
In conclusion, the minimum possible cycle of each operating mode in a case of a device having an address access bus of 30 ns is following.
"CAS LATENCY 3" is a cycle time of 10 ns.
"CAS LATENCY 2" is a cycle time of 15 ns.
"CAS LATENCY 1" is a cycle time of 30 ns.
Now, referring to FIG. 2 which is a logic diagram of the delay circuit 39 shown in FIG. 1, generation of the internal clock signal (5) 40, the internal clock signal (6) 41 and the internal clock signal (7) 42 will be described. As shown in FIG. 2, the delay circuit 39 includes two inverters 49 and 50, three AND circuits 51, 52 and 53, and three delays 54, 55 and 56, which are connected as shown. In addition, level signals CLT1, CLT2 and CLT3 are set by the mode setting circuit 33 shown in FIG. 1 in the above mentioned mode register cycle (for setting the "CAS LATENCY", the burst length, etc.), in order to designate the "CAS LATENCY" mode. The signal CLT1 is at a HIGH level in the "CAS LATENCY 1" mode, and the signal CLT2 is at a HIGH level in the "CAS LATENCY 2" mode. Furthermore, the signal CLT3 is at a HIGH level in the "CAS LATENCY 3" mode. The internal clock signal (5) 40 and the internal clock signal (6) 41 are required in the "CAS LATENCY 1" mode and the "CAS LATENCY 2" mode, but are fixed to a LOW level in the "CAS LATENCY 3" mode. Thus, the timing of generation of the internal clock signal (5) 40 and the internal clock signal (6) 41 is controlled in accordance with a logical level of the level signals CLT1 and CTL2. The internal clock signal (7) 42 is generated on the basis of the internal clock signal (1) 36 in the "CAS LATENCY 1" mode
In the prior art synchronized semiconductor memory device as mentioned above, in response to application of an external clock signal, the internal clock generating circuit is put and maintained always in an operating condition, so that, in a standby condition waiting for application of a command from an external, an electric current is supplied to not only the internal clock generating circuit but also related circuits other than the internal clock generating circuit. Namely, these circuits are always in an operating condition. Therefore, the standby current is relatively large, and the power supply current are wastefully consumed.